1. Field of the Invention
The present invention relates to a multiplying system, and more specifically to a multiplying system for preforming an accumulating multiplication expressed by "A=A.+-.X.times.Y" where "A", "X" and "Y" are in the form of two's complement.
2. Description of Related Art
Conventionally, when the accumulating multiplication "A=A.+-.X.times.Y" where "A", "X" and "Y" are in the form of two's complement) is performed, a multiplication of "P=X.times.Y" is first executed. For this purpose, the multiplier "Y" is supplied to a Booth's decoder, and an output of the Booth's decoder is supplied together with the multiplicand "X" to a partial product generation circuit, so that a partial product is generated. The generated partial product is summed in a partial product summing circuit, so that "P" (=X.times.Y) is obtained. Thereafter, the calculation of "A.+-.P" is performed using an arithmetic unit. For this purpose, an output of the partial product summing circuit is connected directly to one input of a selector and also through a sign inverting circuit to the other input of the selector. An output of the selector is connected to one input of the arithmetic unit, which in turn has its other input connected to a register holding the value "A". Thus, when the calculation of "A-P" is performed, the selector supplies an output of the sign inverting circuit to the arithmetic unit, and when the calculation of "A+P" is performed, the selector supplies the output of the partial product summing circuit to the arithmetic unit.
In the above mentioned multiplying system, when the accumulating multiplication "A=A-X.times.Y" is to be executed, a circuit for inverting the sign of the result of multiplication between "X" and "Y" is required. Therefore, the amount of required hardware is increased, and in addition, the operation speed drops.